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verilog→VHDL変換について

 投稿者:よこっち  投稿日:2009年 1月 8日(木)06時29分4秒
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  はじめまして,よこっちと申します.
ソフトのほうをダウンロードさせていただきまして,早速使用してみたんですが,parse errorが出てしまいました.
おそらく与城さんの一部と同じような状態だと思うのですが・・・

wire exp00a = ( fl_ib[30:23] == 8'h00 ) ;
のとき
wire exp00a ;
assign exp00a = ( fl_ia[30:23] == 8'h00 );
とすればいいんでしょうか??

一応ソースを張っておくので,自分でもがんばって見ますが
もし,お時間があればご指導おねがいします.

/************************************************************************/
/* floating point multiplier (float) */
/* 2006.03.07 */
/************************************************************************/

module fl_multa (
fl_o , // floating output

fl_ia , // floating input a
fl_ib ); // floating input b

input [31:00] fl_ia ; // floating input a
input [31:00] fl_ib ; // floating input b

output [31:00] fl_o ; // floating output

parameter Ofst = 127 ; //parameter: 定数定義

parameter Zero = { 8'h00,23'h000000 } ;
parameter Inf = { 8'hff,23'h000000 } ;
parameter Nan = { 8'hff,23'h400000 } ;

//  function (round to even)
    // step0 ( detect exception )
wire exp00a ;
assign exp00a= ( fl_ia[30:23] == 8'h00 );
wire exp00b = ( fl_ib[30:23] == 8'h00 ) ;
wire expffa = ( fl_ia[30:23] == 8'hff ) ;
wire expffb = ( fl_ib[30:23] == 8'hff ) ;
wire snf_0a = ~|fl_ia[22:00] ;
wire snf_0b = ~|fl_ib[22:00] ;

    // step1 ( multiply )
wire [47:00] snf_1a = { ~exp00a,fl_ia[22:00] } * { ~exp00b,fl_ib[22:00] } ;
wire [09:00] exp_1a = fl_ia[30:23] + fl_ib[30:23] - Ofst ;
wire sin_1a = fl_ia[31] ^ fl_ib[31] ;

    // step2 ( standardize )
wire [47:21] snf_2a = { snf_1a[47:22],(|snf_1a[21:00]) } ;
wire [46:20] snf_2b = ( snf_1a[47] )? snf_2a[47:21] :{ snf_2a[46:21],1'b0 } ;
wire [09:00] exp_2a = exp_1a + snf_1a[47] ;

    // step3 ( round )
wire b_least = snf_2b[23] ;
wire b_guard = snf_2b[22] ;
wire b_round = snf_2b[21] ;
wire b_stiky = snf_2b[20] ;

wire all_1 = &snf_2a[46:24] ;
wire en_inc =  b_guard & ( b_least | b_round | b_stiky ) ;
/******************************************************************
lp Guard Round Sticky operation
0 0 - -
0 1 0 0 round even
0 1 0 1 increment
0 1 1 - increment
1 0 - -
1 1 0 0 increment round even
1 1 0 1 increment
1 1 1 - increment
******************************************************************/

wire [23:00] snf_3a = snf_2b[46:23] +   en_inc ;
wire [09:00] exp_3a = exp_2a        + ( en_inc & all_1 ) ;

    // step4 ( limit )
wire [22:00] snf_4a = ( exp_3a[09] )? 23'h000000 :
( exp_3a[08] )? 23'h000000 :snf_3a[22:00] ;
wire [07:00] exp_4a = ( exp_3a[09] )? 8'h00 :
( exp_3a[08] )? 8'hff :exp_3a[07:00] ;

    // step5 ( exception compensation )
/**** denormalized number not supported ***************************
exp_a snf_a exp_b snf_b exp_o snf_o description
00 any 00 any 00 000000 0   * 0   = 0
ff ==0 00 400000 0   * inf = NaN
!=0 00 400000 0   * NaN = NaN
else any 00 000000 0   * nom = 0
ff ==0 00 any 00 000000 inf * 0   = NaN
ff ==0 00 400000 inf * inf = inf
!=0 00 400000 inf * NaN = NaN
else any 00 000000 inf * nom = inf
!=0 00 any 00 000000 NaN * 0   = NaN
ff ==0 00 400000 NaN * inf = NaN
!=0 00 400000 NaN * NaN = NaN
else any 00 000000 NaN * nom = NaN
else any 00 any 00 000000 nom * 0   = 0
ff ==0 00 400000 nom * inf = inf
!=0 00 400000 nom * NaN = NaN
else any 00 000000 nom * nom = nom
******************************************************************/
function [30:00] fexcpt ;
input exp00a ,exp00b ;
input expffa ,expffb ;
input snf_0a ,snf_0b ;
input [30:00] nom_in ;
casex ( { exp00a,expffa,snf_0a,exp00b,expffb,snf_0b } )
6'b10x_10x : fexcpt = Zero ; // 0   * 0   = 0
6'b10x_011 : fexcpt = Nan ; // 0   * inf = NaN
6'b10x_010 : fexcpt = Nan ; // 0   * NaN = NaN
6'b10x_00x : fexcpt = Zero ; // 0   * nom = 0
6'b011_10x : fexcpt = Nan ; // inf * 0   = NaN
6'b011_011 : fexcpt = Inf ; // inf * inf = inf
6'b011_010 : fexcpt = Nan ; // inf * NaN = NaN
6'b011_00x : fexcpt = Inf ; // inf * nom = inf
6'b010_xxx : fexcpt = Nan ; // NaN * any = NaN
6'b00x_10x : fexcpt = Zero ; // nom * 0   = 0
6'b00x_011 : fexcpt = Inf ; // nom * inf = inf
6'b00x_010 : fexcpt = Nan ; // nom * NaN = NaN
6'b00x_00x : fexcpt = nom_in; // nom * nom = nom
default    : fexcpt = Nan ; // error     = NaN
endcase
endfunction

wire [22:00] snf_5a ;
wire [07:00] exp_5a ;
assign {exp_5a,snf_5a} = fexcpt (exp00a ,exp00b ,
expffa ,expffb ,
snf_0a ,snf_0b ,
{exp_4a,snf_4a});

    // output
wire [22:00] fl_snf = snf_5a ;
wire [07:00] fl_exp = exp_5a ;
wire fl_sin = sin_1a ;

assign fl_o = { fl_sin,fl_exp,fl_snf } ;

endmodule
 
 
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